1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for implementing processors used in reduced instruction set computers.
2. History of the Prior Art
The development of digital computers progressed through a series of stages beginning with processors which were able to process only a few basic instructions in which the programming needed to be done at a machine language level to processors capable of handling very complicated instructions written in high level languages. At least one of the reasons for this development is that high level languages are easier for programmers, and thus more programs are developed more rapidly. Another reason is that up to some point in the development, the more advanced machines executed operations more rapidly.
There came a point, however, where the constant increase in the ability of the computers to run more complicated instructions actually began to slow the operation of the computer over what investigators felt was possible with machines operating with only a small number of basic instructions. These investigators began to design advanced machines for running a limited number of instructions, a so-called reduced instruction set, and were able to demonstrate that these machines did, in fact, operate more rapidly for some types of operations. Thus began the reduced instruction set computer which has become known by its acronym, RISC.
One design of a RISC computer is based on the Scalable Process Architecture (SPARC) designed by Sun Microsystems, Inc., Mountain View, Calif., and implemented in the line of SPARC computers manufactured by that company. One salient feature of the SPARC computers is the design of the processors which include control/status registers and general purpose registers. The control/status registers in the processor of the integer unit, for example, include a processor state register, a window invalid mask, a trap base register, a multiply/divide register, program counters, among others.
The general registers include from forty to five hundred twenty 32 bit registers. Whatever the total number of general registers, these registers are partitioned into eight global registers and a number of sixteen registers sets, each set divided into eight IN and eight local registers. At any time, an instruction can access a window including the eight global registers, the IN and local registers of one set of registers, and the IN registers of a logically-adjacent set of registers. These IN registers of the logically-adjacent set of registers are addressed as the OUT registers of the sixteen register set of the window including both IN and local registers. Thus, an instruction can access a window including the eight global registers, the IN and local registers of one set of registers, and the IN registers addressed as OUT registers of the logically-adjacent set of registers.
This architecture provides a number of advantages not the least of which is that the processor may switch from register set to register set without having to save to memory and restore all of the information being handled by a particular register set before proceeding to the operation handled by the next register set. For example, since the IN registers of one register set are the same registers as the OUT registers of the preceding set of registers, the information in these registers may be utilized immediately by the next or previous sets of registers without the necessity of saving the information to memory and writing the information to the IN registers of the next set of registers. Moreover, the large number of register sets allows a great number of operations to be implemented simultaneously, in many cases without the need to save to memory and restore before proceeding with the operation in any particular register set. This offers great speed advantages over other forms of RISC architecture.
However, no matter how philosophically advanced the SPARC architecture, it requires implementation in hardware.